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Synopsys Synthesizable VHDL LC- 2 Model
Simple programmable processor defined in the popular introductory textbook.

DLX in VHDL
VHDL model of processor; most instructions use 5 clock cycles to run, jumps use 3, floating point timing not fully accurate because fp instructions also take 5 cycles to run; description, download.

Free SPARC VHDL Model Available
Announcement of open source LEON SPARC architecture; Google Groups.

News: Xilinx Acquisition of CoolRunner
Discussion of the Acquisition of CoolRunner by Xilinx

Xilinx on Linux HowTo
An article that describes how to set up the Xilinx tools so that they work on a Linux machine under the Wine Windows emulator.

Using the Xilinx Alliance 2.1i Tools under Linux
A tutorial on how to use the Xilinx Alliance tools under Linux.

Compiling VHDL Designs with Synopsys
Shows how to implement a design using Altera's tools.

ATI's Nucleus RTOS Integrates with Xilinx's FPGA Soft Processor Core
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Xilinx
Programmable logic solution provider. Includes product, services, and market lists, articles, online store, support, career, and investor information.

Microsystems Prototyping Laboratory VHDL Model Collection
VHDL models from Mississippi State University

Synthesizable VHDL Model of 8051
A synthesizable VHDL 8051- microcontroller model, maintained by the Dalton Project of the University of California in Riverside.

VHDL International (VI)
organization dedicated to cooperatively and proactively promoting the Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) as a standard worldwide language for the ...

Software Downloads for "Xilinx Vhdl"

Related: Xilinx Vhdl Software - Xilinx Vhdl Platform - Vhdl Xilinx Software - Xilinx Ise Vhdl - Vhdl Programer Xilinx Free Download

1| 2| Free

m4-la is a Logic Analyzer written in VHDL for the Xilinx ML403 Development board featuring the Virtex4 FPGA. The user interface is written in C for Windows32 based platforms. Xilinx ISE and EDK tools compile the VHDL and MS Visual Studio compiles the UI..

Oscilloscope components, including 100MHz quad A/D, VHDL code for Xilinx FPGA, and driver for Octave or Matlab..

"mprfgen" is a multi-port memory generator that can be used for VHDL designs. It can generate either generic or Xilinx-specific (through component instantiation) multi-port memories. "mprfgen" was written in 2007 and is licensed under LGPLv3..

A tool for the design of reconfigurable systems, implemented as Eclipse Plug-In, mainly for Xilinx FPGAs using the EarlyAccess design flow. Design your system graphically, attach source files (VHDL) and automatically generate (partial) bitstreams..

Full Circuit releases greatly enhanced 'TestBench Tool': Easily create testbenches (VHDL) with this low cost but powerful tool. AUTOMATIC Extracts entity from VHDL source and creates testbench VHDL source. Fills in signal names on tool so that all the user has to do is construct the test patterns. FAST Testbench VHDL source is not changed each time a test is revised (Test patterns are saved to a test vector file) so VHDL is only compiled once. POWERFUL Supports complex formulae for describing signal relationships.

  • Platform: Windows, Mac
  • Publisher: Full Circuit Ltd
  • Date: 18-12-2000
  • Size: 216 KB

Magic Do is a VHDL hierarchy builder that automates the process of generating ncsim/modelsim compilation macro. The same file list can also be reused for synthesis scripts and/or compilation macro for any other simulator. Features 1) Automatically generates compilation macro. 2) Automatically finds and includes required packages. 3) Automatically inserts 87 and 93 option for each file. 4) Provides Alternate folder (optional). 5) Generates unused files and multiple component definition report (optional).

Development of Linux drivers for Xilinx MailBox IP. MailBox IP is a bi-directionnal FIFO plugged between two buses, allowing sending messages from one bus to the other, in both directions..

Signs is a development environment for hardware designs in VHDL and other hardware description languages. It provides synthesis and simulation tools which are fully integrated in an Eclipse plugin including graphical netlist and waveform viewers..

This project contains a set of tools for formal verification and static analysis of VHDL design..

Its a VHDL plugin for Notepad++ which is simular with the one which is available on emacs (Copy a selcted entity port and then paste it as instatiation , Signals or as Testbench ).

Application defines templates of VHDL structures, which allows us comfortly generate most used VHDL structures. It can also work with VHDL testbench templates from which can be created VHDL testbenches of existing projects..

A simple VHDL(VHSIC Hardware Description Language) preprocessor.

ED for Windows is a smart language sensitive programmer's editor, with a breadth and depth of powerful editing capabilities you're unlikely to find elsewhere. Whether you program in C/C++, Progress, VHDL, Fortran, Matlab, Java, PHP, Perl or one of the many other languages ED supports you'll quickly be impressed by its capabilities. ED's intelligent editing features help you to write code by completing keywords and code blocks, inserting user defined code skeletons, and aligning text with its smart and auto indenting.

Alliance CAD System is a free set of EDA tools and portable cell libraries for VLSI design. It covers the design flow from VHDL up to layout. It includes VHDL simulator, RTL synthesis, place and route, netlist extractor, DRC, layout editor..

cIPS is a robust TCP/IP stack for embedded devices.The cIPS library runs without an Operating System and is entirely abstract from any platform. However, it has been fully tested on the Xilinx Spartan 3E Starter Kit..

DGC is a tool for the creation of digital netlists. DGC does an optimization and technology mapping for an abstract description of boolean functions and state machines. Output formats are EDIF, XNF and VHDL. Input formats are KISS, PLA and others. See also: http://gitorious.org/dgc-gtk/.

The dvi_enc is an example of implementation to Xilinx Spartan3A FPGA of the DVI encoder algorithm. It's written by Verilog HDL. And, the implementation supports XGA video mode..

Eclipse Verilog editor is a plugin for the Eclipse IDE. It provides Verilog(IEEE-1364) and VHDL language specific code viewer, contents outline, code assist etc. It helps coding and debugging in hardware development based on Verilog or VHDL..

Plugin Eclipse/VDT supports hardware development in VHDL/Verilog, allowing to easily integrate command-line controlled tools in Eclipse. Underlying Eclipse/ExDT plugin provides integration means that may be used for other languages and applications..

FpgaC compiles a subset of the C language to net lists which can be imported into an FPGA vendors tool chains. C provides an excellent alternative to VHDL/Verilog for algorithmic expression of FPGA reconfigurable computing tasks. More info in wiki..


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